The present invention relates to a method for fabricating semiconductor integrated circuit dies with multi-layered interconnect structures.
A semiconductor integrated circuit of a high integration level comprises a plurality of stacked interconnect layers to define a plurality of sub-circuits having a variety of functions after primitive devices have been formed.
In FIG. 1, there is shown a semiconductor integrated circuit having a plurality of sub-circuits. A semiconductor integrated circuit A shown has a plurality of sub-circuits S1, S2, . . . , Sk (k=6 in the example shown in FIG. 2). Sub-circuits may be large scale functional blocks such as CPU, memory, DSP, AD converter, I/O interface or the like, or may be relatively small scale or basic sub-circuits such as adder, multiplier, multiplexer, flip-flop or the like. In addition , the functional blocks and sub-circuits may be digital circuits, analog circuits or mixed signal circuits.
The semiconductor integrated circuit A has a multi-layered interconnect structure comprising a plurality of interconnect layers (N-layers as shown in FIG. 2). A lowermost layer (the first interconnect layer) provides a wiring connection between primitive devices (transistors) formed in a semiconductor substrate, and is the interconnect layer which defines a basic logic gate, which is an NAND gate or an inverter in the example shown, as shown in FIG. 3. Input and output signal lines for the basic logic gates appear on the stacking surface of the first interconnect layer. Shown within blocks of this Figure which are indicated in broken lines are primitive devices, which do not appear on the surface of the first interconnect layer. The second interconnect layer provides a wiring connection between the basic logic gates which are formed by the first interconnect layer, and is the interconnect layer which defines relatively small scale sub-circuits as illustrated in FIG. 4, for example. Input and output signal lines for the sub-circuit appear on the surface of the second interconnect layer, but logic gates or inverters which constitute such circuits do not appear there. The i-th interconnect layer (3xe2x89xa6ixe2x89xa6N-1) provides a wiring connection between sub-circuits which have been formed up to the (i-1)-th interconnect layer, and is the interconnect layer which defines sub-circuits of a higher scale, and input and output signal lines for the sub-circuits of the higher scale appear on the stacking surface of the i-th interconnect layer. An uppermost layer (N-th interconnect layer) provides a wiring connection between sub-circuits (S1, S2, . . . , Sk) which are formed by the (N-1)-th interconnect layer, and is the interconnect layer which defines a semiconductor integrated circuit A. Only input and output signal lines for the semiconductor integrated circuit A appear on the stacking surface of the N-th interconnect layer, as shown in FIG. 5.
Stacking of individual interconnect layers takes place in a manner shown in FIG. 6. While not shown, a product from an immediately preceding step, namely a substrate in which primitive devices are formed or an immediately preceding interconnect layer is initially subject to a deposition thereon of an oxide layer 11 such as formed by SiO2, as shown in FIG. 6(a).
Photolithography is applied to the oxide layer 11 to define a mask for junctions with wirings or primitive devices located directly below it, and then the reactive ion etching (RIE) technique is applied to form openings 12, as shown in FIG. 6(b). The openings 12 are then filled with a conductive material, for example, tungsten to form junctions (stubs) 13, as shown in FIG. 6(c). As shown in FIG. 6(d), an oxide layer 14 as formed by SiO2 deposition
Photolithography is applied to the oxide layer 14 to define mask and the reaction ion etching (RIE) technique is applied to form grooves 15 for regions to be wired, as indicated in FIG. 6(e). A layer 16 of a metal such as Al, W, Cu or the like is formed as shown in FIG. 6(f), and the metal layer 16 is then subject to a chemical-mechanical polishing (CMP) to expose the oxide layer 14. Wires 17 which fill the grooves 15 form a wiring 17 which is connected to the junctions 13 and also connected to the underlying interconnect layer, not shown, through the junctions 13.
Steps to stack an interconnect layer may follow a procedure shown in FIG. 7. In a similar manner as illustrated in FIG. 6, a condition as shown in FIG. 7(a) is prepared in which junctions 13 fill in an oxide layer 11. Subsequently, a metal layer 16 is formed over the entire surface as shown in FIG. 7(b), and the application of the photolithography and the RIE technique form wires 17 connected to the junctions 13, as shown in FIG. 7(c). An oxide layer 18 is then deposited over the entire surface as shown in FIG. 7(d), and the surface of the oxide layer 18 is planarized by CMP, as shown in FIG. 7(e). In this instance, when openings 12 are formed to provide the junctions 13, the openings 12 should contiguously extend to reach the wires in the underlying interconnect layer.
A method for fabricating a semiconductor integrated circuit with a multi-layered interconnect structure has been briefly described above. In a conventional method for fabricating a semiconductor integrated circuit, there has been no practice of testing primitive devices or sub-circuits which have been already formed in the course of the fabricating steps.
In other words, a test of the semiconductor integrated circuit has taken place by placing a probe in contact with bonding pads of a chip as shown in FIG. 8 after the steps of fabricating a semiconductor integrated circuit chip have been completed to provide an IC in a wafer condition, inputting externally a test pattern to input pads on the circuit under test, and observing a voltage response signal on a power supply pad of the circuit under test or a current response signal through a power supply pad of the circuit under test(wafer probing, die sort). Alternatively, a test pattern is externally input to an input terminal (pin) of the circuit under test and a voltage response signal on an output terminal (pin) of the circuit under test or a current response signal through a power supply terminal (pin) of the circuit under test is observed to perform a test of the semiconductor integrated circuit (package test or final test). Such tests will be hereafter referred to as final tests.
A final test of the semiconductor integrated circuit utilizes a stuck-at fault test, a delay fault test, a quiescent power supply current (IDDQ) test, a functional test, an exhaustive test and the like. The stuck-at fault test is a procedure which assumes a stuck-at fault on a signal line in the circuit under test (which is a fault where a logical signal value on the signal line is fixed to a certain value; a fault in which the signal value is fixed to xe2x80x9c0xe2x80x9d is referred to as stuck-at 0 fault while a fault in which the signal value is fixed to xe2x80x9c1xe2x80x9d is referred to as stuck-at 1 fault) by seeing an influence of a fault through the observation of a voltage signal on an output terminal of the circuit under test with respect to a given test pattern. The delay fault test is a procedure which assumes a delay fault in a signal propagation path or a logical gate in the circuit under test, or a fault that a time interval required for a signal to propagate through the signal propagation path or the logical gate (delay time) exceeds or undershoots a given value (a delay fault in the signal propagation path being referred to as a path delay fault and a delay fault in the logical gate as a gate delay fault), by seeing an influence of a fault through the observation of a voltage transition signal on an output terminal of the circuit under test with respect to a given series of test patterns. The quiescent power supply current test is a procedure which assumes a short-circuit fault across a plurality of signal lines in the circuit under test or a leak fault in a primitive device therein by seeing an influence of a fault through the observation of a quiescent current signal through a power supply terminal of the circuit under test with respect to a given test pattern. The functional test is a procedure which examines whether or not the circuit under test functions properly. The exhaustive test is a procedure which examines output responses of the circuit under test for every combination of signal values to input terminals and flip-flops of the circuit under test. For the stuck-at fault test and the functional test, a description is given, for example, in chapters 6 and 8 of M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, New York, 1990; for the delay fault test, a description is given, for example, in G. L. Smith, xe2x80x9cModel for Delay Faults Based upon Paths, xe2x80x9d Proceedings of IEEE International Test Conference, pp. 342-349, 1985 or C. J. Lin and S. M. Reddy, xe2x80x9cOn Delay Fault Testing in Logic Circuits,xe2x80x9d Transactions on Computer-Aided Design, CAD-6(5), pp.694-703, 1987; for the quiescent power supply current test, a description is given, for example, in S. Chakravarty and P. J. Thadikaran, Intuduction to IDDQ Testing, Kluwer Academic Publichers, Boston, 1997; and for transient power supply current test, a description is given, for example, in M. Sachdev, P. Jamssen. and V. Zieren, xe2x80x9cDefect Detection with Transient Current Testing and its Potential for Deep Submicron ICs,xe2x80x9d Proceedings of IEEE International Test Conference, pp.204-213, 1998 or Y. Min and Z. Li, xe2x80x9cIDDT Testing versus IDDQ testing,xe2x80x9d Journal of Electronic Testing: Theory and Applications (JETTA), vol. 13, No. 1, pp. 51-56, August 1998.
In order to facilitate the testing of the circuit under test, use is also made of a test facilitating design technique, which affords testing functions to the circuit under test such as the technique of built-in self test (BIST) function into the circuit under test, the test point insertion which is intended to improve the controllability and the observability of an internal status of the circuit, the scan design technique, the boundary scan and the like. A description of the test facilitating design techniques is given, for example, in chapters 9, 10 and 11 of M. Abramovivi, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Tastable Design, IEEE Press, New York, 1990.
However, as the circuit integration level rises to a system LSI, for example, in which a memory, MPU, DSP, I/O interface and the like are integrated into a single chip, the number of faults which would be subject to tests such as the stuck-at fault test, the delay fault test and the quiescent power supply current test will be enormous, prohibiting a testing of all of these faults in a practicable length of time. In addition, for the exhaustive test, the number of status corresponding to the number of internal flip-flops increases as an exponential function, making it very difficult to conduct such test. Furthermore, as the circuit scale increases, an increase in the number of functions contained in the circuit under test results in a tremendous figure for the number of test patterns which are required to test every function in the circuit under test.
As described above, if it is desired to test functions of the circuit under test by the final test, an increased length of time is required, and the testing cost of the final test increases. On the other hand, a large scale integrated circuit cannot be subject to testing all of the stuck-at faults, delay faults and short-circuit faults, presenting a problem that a high fault coverage rate cannot be obtained.
What is added is the fact that a rate of increase in the number of pins of an IC package is low in comparison to the rate of improving the integration level of a semiconductor integrated circuit, and this means that an external access to signal lines within the circuit will be further difficult in future, rendering the final test of the semiconductor integrated circuit very expensive.
It is also to be noted that the prior art procedure of testing the semiconductor integrated circuit by the final test involves problems that it is impossible to detect a poor work or a poor function which occurs during fabricating steps, that it is difficult to identify a sub-system which is highly likely to give rise to a fault, and that it is difficult to acquire data on a device level or a sub-system level which are useable in a simulation or a modelling which is intended for purpose of improving a system performance.
On the other hand, the test facilitating design technique, while allowing an external access to be dispensed with or simplified and facilitating a testing of the circuit under test, suffers from drawbacks of an increased overhead for the chip area, a degradation in the performance of the semiconductor integrated circuit under test which is caused by a testing circuit, a fault coverage which is less than desired, an increased length of time required for the test, etc.
Accordingly, there is a need for a testing method which allows the testing cost to be reduced and a testing method which is capable of achieving a higher fault coverage for a large scale semiconductor integrated circuit.
It is an object of the present invention to provide a method for fabricating a semiconductor integrated circuit with a multi-layered interconnect structure which allows a testing cost to be reduced or which allows a fault coverage for a circuit under test to be improved.
In accordance with a method according to the invention, a method for fabricating a semiconductor integrated circuit with a multi-layered interconnect structure by repeating a step of stacking interconnect layers (an interconnect layer stacking step) a plurality of times after primitive devices have been formed is characterized by the inclusion of a testing step of successively testing one or more sub-circuits which have been interconnected up to at least one or more intermediate interconnect layer stacking steps among the plurality of the interconnect layer stacking steps.
With this method, the cost of testing a circuit can be reduced, the fault coverage within the circuit can be improved, and a fault-free semiconductor integrated circuit can be fabricated.
It is desirable that the testing step in the fabricating method for the invention be conducted such that during a first testing step, one or more sub-circuits which have been interconnected up to the preceding stacking step be tested, and during a subsequent testing step, the interconnection between the sub-circuits be tested.
It is also desirable that the testing step in the fabricating method for the invention be conducted such that during a relatively early testing step of a given stack stage, one or more sub-circuits of a relatively small scale which have been interconnected by preceding stacking steps be tested, and during a subsequent testing step for the final layer, a final functional test of an integrated circuit which is finally interconnected be conducted.
It is also desirable that the fabricating method according to the invention includes a CMP (chemical mechanical polishing) planarizing step to planarize a stacking surface before transferring into a succeeding stacking step subsequent to the testing step.
It is also desirable that the fabricating method according to the invention includes a testing of the semiconductor integrated circuit by using the test facilitating design technique in the testing step, and a subsequent removal of a wiring to a testing circuit of the test facilitating design technique which is used in the testing step.
It is also desirable that the fabricating method according to the invention comprises a step of confirming whether or not a given step has been completed upon termination of an interconnect layer stacking step, transferring to the testing step if the completion has been confirmed, and transferring to a next stacking step if the completion has not been completed;
and a step of confirming whether or not the steps of fabricating a semiconductor integrate circuit have been completed upon termination of the testing step and transferring to a next stacking step when the completion is not found.
It is also desirable that the fabricating method according to the invention comprises a step of confirming whether or not a given step has been completed upon termination of a stacking step, transferring to a first testing step which tests a plurality of primitive devices or sub-circuits which have been formed and interconnected up to the given step when the completion is found, and transferring to a next stacking step when the completion is not found; a step of transferring to a next stacking step subsequent to the first testing step; a step of confirming whether or not a given interconnect layer stacking step has been completed after the first testing step, transferring to a second testing step which tests an interconnection for a plurality of wirings between the plurality of sub-circuits which have been connected up to the given stacking step when the completion is found, and transferring to a stacking step which follows the first testing step when the completion is not found; and a step of confirming whether or not steps of fabricating a semiconductor integrated circuit have been completed, and transferring to a stacking step which follows the first testing step when the completion is not found.